This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-324190, filed Oct. 24, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a protection circuit provided in a semiconductor circuit, and more particularly, to a protection circuit for protecting a semiconductor circuit from being broken by static electricity.
2. Description of the Related Art
Conventionally, various protection circuits for countermeasures to static electricity have been typically added to terminals of semiconductor circuits (hereinafter denoted xe2x80x9cICxe2x80x9d) for obviating the ICs from breakage due to the static electricity. Recently, internal circuits tend to be increasingly broken by static electricity applied to an input terminal or an output terminal, which introduces into a power supply terminal supplied with a power supply potential Vcc or a ground terminal (or a reference terminal) supplied with a ground potential (or a reference potential).
For example, in the prior art, a protection circuit formed of MOS elements is arranged between a power supply terminal and a ground terminal for conducting a charge generated by static electricity, which has introduced into the power supply terminal, to the ground terminal.
The conventional protection circuit will be described below with reference to FIGS. 1A to 1C.
FIG. 1A is a circuit diagram illustrating the configuration of the conventional protection circuit; FIG. 1B is a schematic cross-sectional view of the protection circuit; and FIG. 1C illustrates a layout of the protection circuit on a semiconductor substrate.
As illustrated in FIG. 1A, this protection circuit comprises a p-channel MOS transistor (hereinafter denoted xe2x80x9cp-MOS transistorxe2x80x9d) P11, and an n-channel MOS transistor (hereinafter denoted xe2x80x9cn-MOS transistorxe2x80x9d) N11.
The p-MOS transistor P11 has a source, a gate and a back gate connected to a power supply terminal TV which is supplied with a power supply potential Vcc. The n-MOS transistor N11 has a drain connected to a power supply terminal TV, and a source, a gate and a back gate connected to a ground terminal TG supplied with a ground potential GND. Further, the p-MOS transistor P11 has a drain connected to the ground terminal TG.
A general structure of the protection circuit in cross-section is as illustrated in FIG. 1B. An n-type well 102 is formed within a p-type silicon semiconductor substrate 101, and an element region separated by an element separation insulating film 103 is formed in the n-type well 102. A source region (p+-type) 104 and a drain region (p+-type) 105 are formed in the n-type well 102 of the element region. A gate electrode 107 is placed on a channel between the source region 104 and the drain region 105, with a gate insulating film (not shown) therebetween. The p-MOS transistor P11 is formed of these components.
Also, a source region (n+-type) 121 and a drain region (n+-type) 122 are formed within the p-type semiconductor substrate 101. A gate electrode 124 is placed on a channel between the source region 121 and the drain region 122, with a gate insulating film (not shown) therebetween. The n-MOS transistor N11 is formed of these components.
The power supply terminal TV is connected to the source region 104, gate electrode 107 and n-type well 102 of the p-MOS transistor P11. The n-MOS transistor N11 has the drain region 122 connected to the power supply terminal TV, and the source region 121, gate electrode 124 and p-type semiconductor substrate 101 connected to the ground terminal TG. Also, the p-MOS transistor P11 has the drain region 105 connected to the ground terminal TG.
The protection circuit is laid out on the semiconductor substrate as illustrated in FIG. 1C. The source region 104 and drain region 105, which comprise the p-MOS transistor P11, are separately positioned. The gate electrode 107 is arranged between the source region 104 and drain region 105. A source contact 104A is placed in the source region 104, while a drain contact 105A is placed in the drain region 105. The distance between the drain contact 105A and gate electrode 107 is longer than the distance between the source contact 104A and gate electrode 107.
On the other hand, the source region 121 and drain region 122, which comprise the n-MOS transistor N11, are separately positioned. The gate electrode 124 is arranged between the source region 121 and drain region 122. A source contact 121A is placed in the source region 121, while a drain contact 122A is placed in the drain region 122. The distance between the drain contact 122A and gate electrode 124 is longer than the distance between the source contact 121A and gate electrode 124.
However, even though the foregoing protection circuit is added between the power supply terminal TV and ground terminal TG of the semiconductor circuit, internal elements within the semiconductor circuit are still broken frequently. Therefore, electrostatically broken locations are necessarily analyzed in conventional semiconductor circuits to make a different modification to each product.
According to an aspect of the present invention, there is provided a protection circuit comprises a power supply terminal supplied with a power supply potential, a reference terminal supplied with a reference potential, a first p-channel MOS transistor having a gate, a source, a drain and a back gate, wherein the gate, the source and the back gate are connected to the power supply terminal, a second p-channel MOS transistor having a gate, a source, a drain and a back gate, wherein the source is connected to the drain of the first p-channel MOS transistor, the back gate is connected to the power supply terminal, and the gate and the drain are connected to the reference terminal, a first n-channel MOS transistor having a gate, a source, a drain and a back gate, wherein the gate, the source and the back gate are connected to the reference terminal, and a second n-channel MOS transistor having a gate, a source, a drain and a back gate, wherein the source is connected to the drain of the first n-channel NOS transistor, the back gate is connected to the reference terminal, and the gate and the drain being connected to the power supply terminal.